Bipolar complementary metal oxide silicon (BiCMOS) technology combines bipolar and CMOS devices in a single integrated circuit. A BiCMOS digital circuit is made up of both bipolar and CMOS type logic gates. As a result, BiCMOS digital circuits tend to have more than one type of digital signal. For instance, a CMOS logic gate typically generates a digital signal having a relatively large peak-to-peak voltage (Vp-p) equaling approximately the difference between the most positive power supply (VDD) and the most negative power supply (VSS). In general, VDD is equal to 5.00 volts and VSS is equal to 0.00 volts in a typical CMOS circuit. On the other hand, a bipolar logic gate, such as an emitter couple logic (ECL) gate, typically generates a digital signal having a Vp-p equal in the hundreds of milivolt range. In comparing the two signals it can be seen that the DC voltage levels that represent the logic high and low states (V.sub.HIGH and V.sub.LOW) for each of the CMOS and ECL logic gates will be different.
Another factor that determines the V.sub.HIGH and V.sub.LOW for a particular signal is the DC bias voltage of that signal. The DC bias voltage (V.sub.DC bias) of a digital signal is the voltage which the digital signal transitions about. FIGS. 1A and 1B illustrate two digital signals having the same Vp-p but being biased about different bias voltages. Digital signal 10 (FIG. 1A) has a Vp-p equal to VDD and a V.sub.DC bias equal to 0.00 volts. As a result, V.sub.HIGH is equal to VDD/2 and V.sub.LOW is equal to -VDD/2 for signal 10. On the other hand, signal 20 (FIG. 1B) has the same Vp-p as signal 10, but, its VDC bias is equal to VDD/2 instead of 0.00 volts. Consequently, V.sub.HIGH for signal 20 is equal to VDD and V.sub.LOW is equal to 0.00 volts.
Since BiCMOS digital circuits have digital signals generated from both bipolar logic gates and CMOS logic gates, a single BiCMOS digital circuit may have several types of digital signals having various peak-to-peak voltages and DC bias voltages. As a result, digital interconnect lines within a BiCMOS digital circuit may be subjected to a large range of voltage levels. Consequently, a situation that frequently occurs in a BiCMOS digital circuit is that the base of a given NPN bipolar transistor is coupled to an interconnect line that is transitioning between a large range of voltage levels. In the case in which the emitter of that particular transistor is tied to a fixed voltage, the base voltage can become significantly more negative than the voltage on the emitter. When this occurs, the base-emitter junction becomes strongly reverse biased. It is well known in the art, that repeated reverse biasing of a bipolar transistor's emitter-base junction can cause junction degradation and can eventually lead to poor circuit performance or failure.
One particular instance in which this reverse bias condition is prevalent is during a write operation in a memory array. FIG. 2 illustrates a block diagram of a column in a typical static random access memory (SRAM) array along with some peripheral read/write logic. The column of memory cells includes two memory cells (C1, C2). Each cell functions to store a bit of data and the inverse of that data. Each of the cells are coupled to a bit line (BL) and the inverse of the bit line (BL/). Similarly, each of the cells is coupled to a memory cell select line and write line such that only one cell may be selected or written into at a time. BL and BL/are also coupled to a sense amplifier and a word line driver.
The sense amplifier includes two emitter coupled transistors, Q1 and Q2, each having their base coupled to BL and BL/, respectively. The sense amplifiers also include a resistive load, R, coupled between each of the collectors of the transistors and VDD and a current source coupled between the emitters of the transistors and VSS. The write driver includes two CMOS inverters, INV1 and INV2.
The typical prior art operation of the SRAM shown in FIG. 2 is that during a read operation, both of the CMOS inverter write drivers, INV1 and INV2, are "off". That is, a voltage corresponding to a low logic state is applied to the input of each inverter and the output of each inverter is at a voltage corresponding to a high logic state. Generally, the voltage level corresponding to a CMOS inverter high logic state is equal the most positive power supply in the circuit (referred to as VDD). Further, the voltage level corresponding to a CMOS inverter low logic state is equal to the most negative power supply of the circuit (referred to as VSS). Typically, VDD is equal to 5.00 volts and VSS is equal to 0.00 volts. Thus, during a read operation, the write drivers are pulling both BL and BL/to a voltage equal to VDD. Also during a read operation, one of the memory select lines is selected and the data stored in the accessed memory cell is passed to each of BL and BL/such that the memory cell drives one bitline "low" and the other "high". In doing this, the memory cell attempts to pull either BL or BL/towards VSS, (depending on the data stored in the memory cell). However, the write drivers are designed to be much stronger than the memory cell. As a result, the voltage on the "low" bitline is held clamped at a voltage slightly lower than VDD (typically around 200.00 milivolts below VDD) while the high bitline is driven to VDD. Thus, during a read operation for the SRAM shown in FIG. 2, BL and BL/transition between a voltage equal to VDD (a "high" logic state) and at a voltage slightly less than VDD (a "low" logic state).
During a write operation in the SRAM array shown in FIG. 2, one of the CMOS inverters are enabled and one is disabled--depending on the data to be written into the cell. As a result, one of the bitline pairs is driven to a CMOS high logic level (VDD) and the other is driven to a CMOS low logic level (VSS). By driving BL and BL/to these voltages the write driver is able to change the state of the memory cell. However, in driving one of the bitlines to VSS, an undesirable condition occurs. Specifically, if one of the bitlines, for example BL, is at a voltage equal to VSS and the other, BL/, is at a voltage equal to VDD, then the voltage applied to the base of Q1 is equal to VSS and the voltage applied to the base of Q2 is equal to VDD. In this state, the emitters of both sense amplifier bipolar transistors are at a voltage equal to one diode drop less than VDD (i.e. VDD-V.sub.BE). With VSS applied to its base and VDD-V.sub.BE applied to its emitter, the base-emitter junction of Q1 is strongly reversed biased.
One manner in which circuit designers presently avoid this reverse bias condition, whether in an SRAM circuit or in any general circuit design, is to avoid using a combination of small swing/large swing signals on the base of any bipolar transistors within the design. Designing a circuit in this way eliminates any chance of base-emitter junctions becoming strongly reverse biased. However, this technique can be very limiting in BiCMOS circuit designs.
One generally known method utilized to avoid subjecting certain interconnect lines to undesirable variable voltage level signals is to isolate or decouple the interconnect line from the source of the signal. FIG. 3 illustrates a typical prior art isolation circuit. The isolation circuit shown in FIG. 3 includes decode logic 40 and transmission gates (T1-T4) coupled between the variable voltage signal 41 and each of the interconnect lines, I1-I4. Control signal 42 (generated from another portion of the logic circuit) designates which interconnect line is to be decoupled. Typically, the control signal corresponds to specific operations or synchronized events occurring within the circuit in which particular interconnect lines need to be decoupled. Decode logic 40 decodes the control signal and couples a disable signal on the control terminal of the corresponding transmission gate of the designated interconnect line. The main disadvantage of this type of isolation circuit--particularly in large scale integrated (LSI) circuit designs--is that the decode circuitry is typically implemented with numerous gates. As a result, decode logic 40 can potentially add many gate delays to the integrated circuit while consuming large amounts of chip space. In addition, more logic may be required to generate the control signal.
The present invention is a protection circuit that automatically senses when a variable voltage level signal coupled to an interconnect line has reached an undesirable DC voltage level and then isolates the interconnect line from the voltage. The advantage of the present invention is that it responds to the specific voltage level on the interconnect line and not to other event controlled signals originating within the logic circuit as with the prior art. Thus, the present invention is a self-contained isolation circuit, that requires no additional logic. In addition, the level sensing feature of the present invention allows circuit designers to isolate interconnect lines from different voltages. For example, while one line may be isolated from one particular voltage level, another may be isolated from another voltage level. Finally, since the present invention does not require decode circuitry, such as the prior art, it is more space efficient and tends to have less gate delays.